null
@Marc103
null
@Northwestern University
null
@BiV
undefined
null
mferreira103301@gmail.com
https://marc103.github.io/
Chicago
Available for hire
CV
Floating-Point-Image-Processing-SV-RTL
Image processing modules done in custom area efficient floating point.
SystemVerilog
Image-Processing-SV-RTL
Features a Convolution Filter and Bilinear interpolator written and tested in System Verilog, using adjustable Fixed Pointed Arithmetic.
SystemVerilog
OV7670-with-FPGA-and-Demosaicing
Interfacing with the OV7670 camera, demosaicing and outputting to VGA display
SystemVerilog
LC-3-Verilog-Implementation
Implemented the LC-3 ISA specifications in verilog.
Verilog
Forks.