Image-Processing-SV-RTL

Features a Convolution Filter and Bilinear interpolator written and tested in System Verilog, using adjustable Fixed Pointed Arithmetic..

  SystemVerilog   0   0

OV7670-with-FPGA-and-Demosaicing

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  SystemVerilog   1   0

LC-3-Verilog-Implementation

I will be implementing the LC-3 ISA specifications in verilog.

  Verilog   4   0

Floating-Point-Utilities-Chisel

Parameterized Floating Pointer Adder, Multiplier and Divider, written using Chisel DSL.

  Chisel   0   0

RV32IM-zicsr-SV-Implementation

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  SystemVerilog   1   0